1. Field of the Invention
This invention relates to electronic devices having metallization patterns formed on at least one surface thereof, and to methods of forming such patterns. to give a particular example, the invention relates to a beam-leaded semiconductor chip which has a metallization pattern including elements of two different thicknesses. Such a chip has, for instance, a gold plated pattern of conductors on the surface of the chip itself. From this pattern, beam leads extend beyond the body of the chip. The beam leads are also usually formed of gold, however, they are substantially thicker than the conductors on the chip.
2. Description of the Prior Art
One of the techniques employed in the semiconductor industry for joining semiconductive chips to substrates is thermocompression bonding of beam leads extending laterally from such chips. The chips are manufactured from a semiconductor slice or wafer which is ultimately separated into individual chips. After the chips have been separated from the wafer, they are usually mounted to substrates. The substrates have conductive patterns to which the beam leads of the chips are bonded. External leads are also bonded to such patterns to connect the resulting chip assemblies into larger circuits. The beam leads are therefore used to physically mount the chips and to electrically connect the chips to the more rugged external leads.
U.S. Pat. No. 3,426,252 to M. P. Lepselter discloses a beam lead structure and methods of forming beam lead metallization patterns. In summary of the Lepselter technique, platinum silicide is first formed at each opening in an insulating surface of a semiconductor device bonded in a wafer. A layer of titanium and then a layer of platinum are deposited on the wafer. A gold pattern including the beam leads is formed on the surface of the platinum layer with the aid of conventional photoresist masking. Openings are formed in the photoresist mask. Through these openings gold is selectively plated to form an interconnecting pattern and the beam leads, all to the same thickness. After removing the photoresist mask, the platinum and titanium layers which are not protected by the gold pattern are then removed by conventional back sputtering techniques.
U.S. Pat. No. 3,388,048 to J. M. Szabo discloses another manufacturing method involving beam leads. According to the Szabo disclosure, the beam leads and interconnecting conductors on the surface of the chip are plated to two different thicknesses. In preparation for a selective plating step which does not involve masking, the platinum film and then the titanium film are selectively etched to completely remove the material of each film from the surface of the wafer with the exception of the area of a base on which the gold interconnecting conductors and beam leads are disposited. The portions of the base on which the beam leads are to be formed are electrically separated from the remainder of the base by respective gaps. The beam-lead portions of the base are then electrically connected through the wafer to form cathode electrodes in a plating circuit. Initially, only the connected beam-lead portions of the base are gold plated. However, once the deposited gold on the beam lead portions bridges the gaps and contacts the interconnecting portions of the base, these portions are also plated. The beam lead portions continue to be plated to achieve a desired greater thickness than the interconnecting portions. A difficulty with this prior art process is to accurately control the time at which the various gaps in base become electrically bridged. Any variation in gap widths, for instance, would naturally result in a deviation from a desirable difference in the thickness between the interconnecting conductors and the beam leads.
A particular metallization technique which has been adopted by the industry is described in an article in the December, 1967, issue of The Western Electric Engineer. The article, beginning on page 2 of the referred-to issue, entitled "Manufacturing Beam-Lead Sealed-Junction Monolithic Integrated Circuits" by S. S. Hause and R. A. Whitner, discloses a combination of photoresist masking steps and of gold plating steps according to which the beam leads are formed independently of the remaining pattern of the wafer. While the method described in the above article reflects the current art of forming conductive interconnecting paths and beam leads on wafers, some problems are connected therewith. The problems appear to stem from faulty photoresist masking. Such faults in masking may, for instance, occur because of the presence of dust particles on the surface of the wafer during processing of the photoresist. The problems are evidenced by occasional plating defects, such as gold nodules and cross-connections between adjacent conductors. While only a small percentage of the chips in process are affected by such plating defects, it is nevertheless desirable to minimize, or eliminate entirely, these defects.